This application claims priority to Great Britain Application Serial No. 0025104.1, filed Oct. 13, 2000 (TI-30971GB).
The technical field of this invention is that of peripheral control in a computer system.
This invention relates to an Integrated Device Electronics (IDE) controller interfacing a computer bus to an IDE device. The IDE standard governs the exchange of data between a computer bus and the IDE peripheral. The typical IDE peripheral is a hard disk drive. In the IDE standard various control functions are accessed via task registers which are memory mapped into the address space of the computer bus.
Task registers in IDE devices are accessed individually and in series. A read or write of a single register can take as long as 600 ns in ATA mode 0. These task registers are generally mapped into the system address space. A read or write at a particular address will be recognized by an IDE controller as a request to access a particular IDE device task register. This IDE controller will initiate a sequence of operations to access the addressed task register. In the case of a task register read, the computer bus and the device requesting the task register access, which is typically a computer central processing unit (CPU), will be tied-up waiting for the task register access to complete. In the case of a single data write, the IDE controller may buffer the data to be written to the task register upon receipt and release the bus. The write can be completed in the background by the IDE controller. In the case of a data read there is an additional delay for the data stored in the task register to be returned. A series of back-to-back task register writes experience similar lock-up periods as a series of reads, because each new write cannot begin to the IDE device until the previous write has completed. The time taken to complete a write is about the same as that for a read. In either case a task register access can lock-up the computer bus and the other device for many cycles. This cycles represent wasted performance at today""s computer system speeds. As system speeds increase in the future, the number of wasted cycles can only increase.
This disclosure describes an enhancement to an IDE controller which allows multiple task register access requests to be quickly initiated. These requests are then completed by the IDE controller without locking-up precious system resources. An indication of their completion is then made available. In the case of multiple task register reads the read-data can then be read at a time convenient to the system.
The method maps at least one intermediate data register of a first data width into the address space of the computer bus. The computer bus writes data to an intermediate data registers with write strobes corresponding to data subsets of a second smaller data width equal to the data width of the device registers. The IDE controller then transfers data from the intermediate data register to the device registers in subsets of the device register data width. The subsets transferred correspond to write strobes. This data transfer employs a fixed order of device registers.
A write status data field of one of the intermediate data registers enables tracking the data transfers. This write status data field is initially written to a first digital state corresponding to the write strobes. Each bit is changed to the opposite digital state upon completion of transfer of data from the intermediate data register to the device register. The IDE controller may issue a selectively enabled interrupt when all the bits are in the opposite digital state upon completion of the data transfer. The IDE controller may also set a completion bit.
For reads of the device register, the computer bus writes data to a read selection data field of an intermediate data register. Each bit of the read selection data field corresponding to one device register. The IDE controller transfers data from the device registers corresponding to bits of the read selection data field having a predetermined first digital state to an intermediate data register. The device register data may then be read from the intermediate data registers via the computer bus. This device register read has a fixed read order of device registers. The individual bits of the read selection data field are changed to an opposite digital state upon completion of transfer of data the said device register to the intermediate data register. Upon completion of the data transfer the IDE may issue an interrupt or set a completion bit.